DigSys blog

___________ Agenda and important dates __________________ Digsys

Term 18-19 Q1

January 17 (13.00)

Due date to upload at Atenea the task corresponding to the P_Ch3 cooperative project [10% Oral presentation + 2.5%· Written Report].

January 8

Final-term exam.

December 20

During the last 25 min. of the class, we’ll solve the Questionnaire #3.1 about P9-P10-P11: introduction to microcontrollers. Same conditions as usual.

December 13

Hand in the preparatory laboratory assignment PLA  #3.1 on designing the P9 Adder_BCD_1digit. In this Problem 9.3 there are more details.

December 5

During the last 25 min. of the class, we’ll solve the Questionnaire #2.2 about P6, P7 and P8: FSM, counters, registers, advanced applications. Same conditions as always.

During the last 25 min. of the class, we’ll solve the Questionnaire #2.1 about sequential circuits and FSM on P5 and P6. Same conditions as always.

December 4

Hand in the preparatory laboratory assignment PLA  #2.2

November 28

 

November 27

Hand in the preparatory laboratory assignment PLA  #2.1

 

November 14

During the last 25 min. of the class, we’ll solve the Questionnaire #2rec about combinational circuits on P1, P2, P3 and P4 to have a second chance for the EXA_1 P2. It is an individual exam and you must be in classroom in order to be graded. Take to the classroom your portable computer / tablet / smartphone to solve the test through the Atenea platform. Only one attempt will be permitted. Paper, pen and a basic calculator will be required to solve some questions.

 

November 13

Hand in the preparatory laboratory assignment PLA  #2

There have been a mistake for some days and the problem collection weren’t updated correctly. Precisely the problem 2.4 was rewritten to make it more readable.  Sorry for the inconveniences,

 

November 7

Mid-term exam. This is the assignment and proposed solutions.

October 24

In the intranet ATENEA you have the link to the mid-term polls so that you can give your anonymous opinion on how the course is going on up to now. In this way we still have time to make amendments if necessary for the next second part of the course. Thank you in advance for your interest and collaboration.

During the last 25 min. of the class, we’ll solve the Questionnaire #2 about combinational circuits on P3 and P4 (remember that CSD is a ladder and everything in Chapter I may be expected). It is an individual exam and you must be in classroom in order to be graded. Take to the classroom your portable computer / tablet / smartphone to solve the test through the Atenea platform. And a calculator. Only one attempt will be permitted.

October 16

Hand in the preparatory laboratory assignments PLA  #1

October 10

During the last 25 min. of the class, we’ll solve the Questionnaire #1 about combinational circuits on P1 and P2. It is an individual exam and you must be in classroom in order to be graded. Take to the classroom your portable computer / tablet / smartphone to solve the test through the Atenea platform. Only one attempt will be permitted. This is a sample questionnaire for you to  study.

September 13

Very welcome to the CSD course on digital electronics. In order to follow the course, there is weekly planning of every session.

We’ll answer your emails, only if you follow these rules. This is our timetable in case you like to ask questions or have some tutorial time.

This is the course starting point: P1.  This is the blog where you can attach your questions and answers and discuss with your colleagues and us. Simply ask for subscription and we’ll authorise you when logging in from a UPC address. Edit the corresponding post or its comments to write your queries.  There will be up to 12 posts named from P1 to p12 during the course.

Term 17-18 Q2

June 18

Exam 2 CSD (300022), 17:00 – 18:30, 132V / 133V. This is the exam (docx) (pdf) and a discussed solution.

The 10% of the final grade related to attitude and participation will be assigned to you in this way: Lab attendance 40%, Exams passed 30%, Projects passed 30%. Thus, for example, if someone has attended all the lab sessions, and has passed only one exam and two projects, their grade will be a 4+1.5+2 = 7.5 (0.75 of the final grade).

June 17

Due date for the P_Ch3 is June 17. This is the correction sheet. Check all the project details at the Atenea.

NOTE: If your video file is too large in size, do not upload it at Atenea. Upload the  video file to any platform of your convenience, and attach a text file in Atenea containing only the link to the video file, so that anyone can watch it. Check that the link will works fine for us (because if not, you have a problem!).

May 21, 8 AM

  • We’ve been asked to delay the P_Ch2 due date: The new due date is Monday 21 8 AM.

May 18

Due date for the P_Ch2 is May 18. This is the correction sheet.

May 16

A second chance for marking in P#2.

Hi,

We’ve been correcting your individual project P#2 on the design of the BCD_Counter_mod60. And there is a problem because most of you have not understood what the project was about. Most of you handed in RTL schematics, simulation results and VHDL files. However, they cannot be marked because you have not presented (or it contain too many errors) a detailed plan explaining the way such circuits were inferred in successive phases as it was annotated in the blog entry May 8 or discussed with students who asked about it in office time.

Besides, this P#2 is necessary to invent later the P_Ch2 Timer_HHSS using similar procedures. So better if you pay attention to their design phases.

So, please, redo and hand in again by Wednesday 16 in the lab class the missing planning so that you can pass the P#2 and get some marks. It should be as follows:

  1. The explanation on how the Counter_mod16 works (it is not necessary to develop and test it because it was a tutorial available in digsys).
  2. How to build a truncated counter such as the Counter_BCD_mod10 using one component Counter_mod16 and logic.
  3. How to chain or expand counters such two Counter_BCD_mod10 to implement a larger counter such as a Counter_BCD_mod100.
  4. Finally, how to truncate such counter to implement the

*** The meaning of a quality report is that you can use it to teach your peers or even professional engineers. A good report is ready to prepare slides for an oral presentation or to type it in a word processor.

May 9/10

P#2: Proposed individual exercise. Due date: May9/10 in the laboratory session: Once studied the Hour_Counter example in P7, solve a BCD_Counter_mod60, the circuit that is included as a component in the Counter_MMSS in P_Ch2.

May 8

During the last 25 min. of the class, we’ll solve the Questionnaire #3 about sequential circuits. Take to the classroom your portable computer / tablet / smartphone to solve it through the Atenea platform. Only one attempt will be permitted.

April 29

Today the server DIGSYS is down for some technical reason. Use the alternative page at this address.

April 9

Exam 1: This is the exam EX1 (pdf) and a discussed solution. This is the Problem 1 truth table in Minilog format.

March 26

Due date for the P_Ch1 is March 26. This is the correction sheet.

 

March 20

During the last 25 min. of the class, we’ll solve the Questionnaire #2 about combinational circuits. Take to the classroom your portable computer / tablet / smartphone to solve it through the Atenea platform.

March 14

P#1: Lab session for assessing the 3 following projects:

1.- Circuit_W (or Circuit_C) using the method of decoders.

2.- Adder_1bit using the method of multiplexers and MUX_2.

3.- Circuit_K using the method of decoders.

During the last 25 min. of the class, we’ll solve the Questionnaire #1 about combinational circuits.

March 8:

The list of projects studied in P3. P2, and P1.

 

February 12

CSD: The first class of the term will be held the next Tuesday February 13, 8.00 AM, at room C4-026V.

____________________________________

February 9

Hem explicat els fonaments dels circuits digitals programables una altre vegada a un institut de secundària. Aquí teniu les transparències que representen una introducció en línies generals a CSD.

February 5

Hem impartit aquests dies un taller demostratiu d’introducció a les xarxes de sensors sense fils a estudiants de Batxillerat. L’hem col·locat en el context d’aquest projecte P17 del curs d’inicialització a la Raspberry Pi disponible en aquesta web. Si voleu aprendre sobre aquest micro-ordinador i també sobre l’Arduino no és necessari que us apunteu a cap curs ni que pagueu diners, simplement heu de seguir els projectes descrits en mode autoaprenentatge.

 

Term 17-18 Q1

January 16

Important note: Let’s give the last project P_Ch3 some more days. The new due date will be on Saturday 20 at 15.00.

 

January 12

This is the EX2 and this is a possible draft solution showing the main issues and how the problems can be solved. If you have doubts on any problem, please, take your time and try to solved it yourself.

The 10% of the final grade related to attitude and participation will be assigned to you in this way: Lab attendance 40%, Exams passed 30%, Projects passed 30%. Thus, for example, if someone has attended all the lab sessions, and has passed only one exam and two projects, their grade will be a 4+1.5+2 = 7.5 (0.75 of the final grade)

I’ll be here in office or at the school all the time, so, please, ask me as many questions as you like to solve the P_Ch3. And, if you choose the option 4B about a 10 min. oral presentation, it can be about any problem solved during the course. I’ll recommend you this option 4B, unless you have a complete comprehension of Ch3.

December 22

  • List of projects to design the P_Ch3 as a sequence of steps.
  • List of projects studied in P10 on how to solve sequential systems in microcontrollers using the FSM approach and the C language. Interrupts to detect signal edges.
  • List of projects studied in P9 on the introduction to microcontroller’s architecture, program flow, RAM variables, C language and compiler, basic I/O, reading (pooling) signal levels and writing voltage values, etc.

 

  • Exam2 on Ch2 and Ch3:

  • Deadline for the P_Ch3 on the Timer_MMSS based on a microcontroller ATmega 8535: January 17 23.00.

 

December 13

Benvolguda professora, benvolgut professor,

Recordeu que encara estan obertes les enquestes oficials de la UPC d’aquest quadrimestre. Us informem que el vostre centre ha decidit ampliar el termini per contestar les enquestes fins el 22 de Desembre. Us animem a que feu difussió entre els vostres alumnes per tal d’assolir una bona participació.

Per tal de tenir una participació elevada us demanem un cop més la vostra col.col·laboració. Cada assignatura de teoria hauria de dedicar uns minuts de classe a què els alumnes responguin les enquestes de l’assignatura que s’està impartint i les dels seus professors.

Els alumnes han rebut els correus informatius, i poden accedir a les enquestes a través d’Atenea, però és important que els faciliteu també a classe l’enllaç corresponent (https://e-enquestes.upc.edu )i que els recordeu els diversos motius pels quals és molt important la seva participació.

Moltes gràcies per la vostra ajuda.

Salutacions cordials,

eetac.planificacio@upc.edu

 

December 11

December 10

NOTE: Citrix virtual has not been working for two days now. It cracked or hanged on Saturday and it cannot be accessed. There is no maintenance service on weekends and it has to be repaired next Monday. So, we’ll delay de P_Ch2 due date by Thursday 14 at 13.00.

Sorry for the inconveniences and regards,

Francesc

 

December 4

  • E-enquestes. We need yo know what you are thinking on the course content and development in order to try to do it better. Thank you for your participation.

November 28 & 29

Organising P8 (P-Ch2). This is the organisation and assessment checklist. Thus, working in your cooperative group, you can go step by step solving one at a time the different circuits involved in the project. Ask questions when necessary. Due date by December 11.

November 25

November 23 & 24

Extra classes on problem solving. Let’s solve problems on counters.

November 16 & 17

Extra classes on problem solving. Problems on asynchronous circuits to better comprehend how the 1-bit memory cells works.


November 6

October 31

  • This is the P_Ch1 rubric for assessing the project.
  • Due date for the P_Ch1: 10-bit adder/subtractor.

September 6

  • Classes will start by September 13 at 026V (3GM1) at 8.00, and at 336V (3GT31) at 19.00

July 21

  • CSD assessment system has changed from previous course editions. Here in this presentation there are some details.

 


Course 16-17 Q2

June 20

Your proposed CSD final grade has been upload as “Final_p” at NetArea.

June 13

Yet another note after email discussions with you now at night-time : New due date for P12 is Monday 19 from 12.00 to 14.00 at lab 129B.

No problem. We all understand that our main goal here in this business is to pass as many subjects and with the highest grades as possible. Moreover, in this way, as you say, some of you will try to develop the project even with more attention, which as you know is what I’ve been pretending all the course.

I’ll still have some hours left for fixing the final CSD grade for all of you. On top of that, students can still try to meet me before the due date, as usual.

Remark: Now there is only P12 (4%) , eP2 (7%), AP (10%) presentation, and my final 6% (attitude and participation) left for marking, thus calculate yourself your current mark or ask me for it, and be smart trying to do your best for passing CSD.

Note: P11 and P12 are not going to be downgraded when considering the IT3 marks.

Remember that P12 will be corrected by Friday June 16 in lab 129B from 16:45 to 18:00, unless you like to contact me before this due date. And, like in P11, even if it’s a group mark, all the team members have to be in the lab ready for answering questions about the project.

June 9

This is the ePortfolio page where to find the eP2 assessment sheet.

And this is where to find information on how to proceed to produce a 10 min cooperative group video presentation of one of your course projects (AP). Presenting in English counts up to 20%.

This is the second chance IT2 and IT3.

June 8

My group and I have a question about deliver of P11. We like to know if all the members of the group have to come to deliver the project?

Answer: It is better if you are the three students of the cooperative group. Because if necessary, I can ask questions to you to infer which has been your personal involvement in the project development.

June 7

In case you’ve not been able to see me in office, after the second chance IT1-IT2 test, by June 9, I’ll be in lab 129B for handing in your P11, from 16:45 to 18:00.

The same for Friday June 16, in lab 129B from 16:45 to 18:00 for handing in your P12.

By June 19, upload the oral presentation (video) of the project you have chosen (AP) on your ePortfolio, and send me by email your assessment sheet eP2.

 

May 31

You’ve got published the IT3 and the preliminary mean mark for the projects P5-P8 (P5-P8p) taking in consideration your IT2 result.

Second chance exams for IT2 and IT3 is:

Thus, let’s continue working to see if in the end we can pass all.

May 30

Thank you very much for your participation in the UPC questionnaires. They are still open until tomorrow if you like to add more comments. Your opinions are very important for us and the school staff. They are necessary for evaluating our studies and try to do it better the next term.

This is today’s IT3 with the initial introduction and also a project solution ready for running in the Proteus virtual laboratory. Here you are also an example of timing diagram for the question 8. In this way you can compare different technologies and procedures to implement the same application. It was solved in IT2 designing hardware using VHDL and synthesising the circuit in a PLD/FPGA. Now in Chapter 3 we solve it programming a microcontroller in C.

Comparing solutions arises a new set of questions that cannot be easily solved in this introductory CSD course, for instance:

– Which circuit is faster?, for instance, allowing you to build a sequencer at 400 MHz CLK?

– Which has less power consumption and can operate using a single button battery of 1.2 V?

– Which is cheaper and occupies less PCB board?

– Which can be easily enhanced with new features like remote control?

May 29

Question: How to prepare for IT3?

Answer: As the others, IT3 is NOT an exam. It’s a simple test to see how well you have solved and completed all the sections in the P9 and P10 tutorials and projects. The only valid and effective preparation for IT3 is:

1.- Run/study/analyse and take your own notes from the tutorial Dual_MUX4 in P9.

2.- Specify/Plan/Develop/Test the P9 BCD_Adder in the described mode of operation.

3.- Run/study/analyse and take your own notes from the tutorial BCD_Counter in P10.

4.- Specify/Plan/Develop/test the P10 Johnson_counter in the described mode of operation. .

5.- Study and solve (if you like it or have more time) any other project available in the CSD web or elsewhere in the usual way: trying to adapt them to the templates in P9 or P10. For instance, to continue with P11 and P12 you must be in this section 5. As you’ve seen, CSD is a ladder where you have to climb only one step at a time. In this fashion, you’ll fully comprehend the subject and be empowered to solve small but quite complex digital systems any time. This is an example bachelor final thesis in this line from Alberto Gómez and here you’ll find more examples.

 

May 23

May 17

  • IT3 is scheduled by Tuesday 30.It will contain basically content on P9 and P10. See examples from other semesters.

 

  • IT2 is scheduled by Tuesday 23. It will contain questions from P5 to P8. See examples in this blog from previous semesters.

I know that working with projects may have left you worried about whether you have learned it all. Project based learning is not linear, and, naturally some people will have a better understanding of some chips than other people in class, who will be expert in other chips. You must have specified and planned them all, but only developed and tested some of them. The test will fair in this respect.

 

  • More on the questionnaire:

May 15

  • From now on you are invited to fill in the UPC questionnaire. We appreciate very much your opinions and general comments on the subjects you are matriculated.

  • Today, we’ll meet at room 028b to solve your doubts in P7 and P8.

May 5

Let us schedule the remaining due dates:

Projects: P7 and P8 : May 17; P9: May 24; P10: May 31; P11: June 9; P12: June 16.

The oral (video) presentation of project: June 19

ePortfolio sheet eP2: June19

Preview of the final grades: June 21

I like to remind you that in additional to the usual office time, we can have extra classes or tutorials in group any time if you find it necessary for solving questions about the projects. Remember that the better you understand the project and the planning the easier is the development, testing and documentation.

May 2

“digsys.upc.edu” is fully functional again.

May 1

NOTE: The “digsys.upc.edu” server cracked or hanged today. You see, our systems are not very reliable … Sorry! (I have to wait until tomorrow to see what happened). So I’ve copied the web to this address in an emergency way to solve this crucial problem: http://1747.83.113.110

So, simply type it in your browse, and you’ll see the web again, I hope so. I have to have redundant servers (in this case a simple Raspberry Pi) to be sure that you can access any time the CSD information. Thanks for warning me of the problem.

April 18

The new due date for assessment sheet (eP1) on the materials of your portfolio is Thursday 20.

March 31

This is the second chance IT1 and some discussion here.

March 27

I’ve got in my office your P4 corrected. You can pick it up for any comments and to upload it at your ePortfolio. Remember that the final validation of the P1 … P4 project grades depends on you passing your individual test IT1. There is a second chance by March 31 at:

March 21

Generate a group ePortfolio using the Google Sites tool and this instructions and send me the link by email, so you’ll have an archive location to store your projects and reflection produced in this CSD course.

Later on, by April 18, you’ll be required to send me this assessment sheet (eP1) on the materials and reflections archived by your cooperative group.

NOTE: You can scan yourself your projects and tests sheets and convert them to PDF files in any of the EETAC printers at no cost. If instead, you go to the reprografia centre at the CBL library building, you have to pay: a) If you have a USB –> 0.05 €/sheet; b) If the scanned files have to be sent by email or uploaded to a web page, –> 0.05€/sheet + 0.75€ additional.

March 12

  • The IT1 exam is scheduled for Tuesday 21 (45 min max).

February 12

  • The course agenda is quite simple: let’s design a project every week. After the P4, will sit for an individual test IT1 on projects P1 … P4.
  • First CSD class at room 022B. This is the first project P1. And here is where the discussion will be located.

February 10, 17

  • Seminari sobre la Raspberry pi a l’ICE – UPC.

February 1

  • “Dissenys i aplicacions amb circuits digitals programables”, xerrada de presentació de la matèria de sistemes digitals per als estudiants de batxillerat. INS El Pedró, l’Escala. Pla de promoció dels estudis de la UPC. (1: pptx, pdf), (2: curs més detallat html), 2010 – 2016.

Course 16-17 Q1

January 13

  • Cooperative group video recording of an oral presentation of a course project (10%): January 19. Check that anyone (for instance, me) can open the video file and watch it without any problem, because if I have a problem to watch it it cannot be assessed.
  • The ePortfolio eP2 self-assessment sheet (7 %) : January 19. (send it to me by email as you did for the eP1).
January 11

  • Remember that the due date for the P12 is January 16. For instance, from 10.00 to 13.00 (email me if you have to attend in another time during the day). In addition to the documentation, grading also implies the reviewing of your project files, folders and program execution.

January 10

  • This is the IT2-IT3 second chance exam. As you see, the very same idea of a dedicated processor controlled by a FSM can be applied once and again to solve many projects in the industrial or telecommunications domains. And for the many not very demanding projects, once the specifications and the general planning are discussed, there is the option to develop them using CPLD/FPGA (Chapter II) or microcontrollers (Chapter III).

January 9

  • Grading the remaining projects will be conducted as usual, you have to upload them as the other ones. And you have to show and explain them to me too, in office time or for instance tomorrow during the second chance exam (10.30 -12.00, 130G).

December 31

  • NOTE: Drive <L:\>is in operation again.
  • Can we report the P11 and P12 using a word processor? I mean, doing the same structure and the same things, but all in “word”(with our names in each page or something like this). All these because if we have to show to you all this two projects in the e-portofolio, we can save time for not having to scan all the project pages, and also save ink because we don’t have to print all the code and pictures. What do you think?

Yes, I agree, it’s a good idea to finish the last projects using a word processor instead of pen and paper. Right. I should have given this option to everyone, if only I had remembered. I’ll annotate it in the agenda in case someone else wants to do it. We’ll meet in office by the due date to review and correct them as usual. This is a Word template with some features that you can use to write your report taken from this former CSD unit which I have yet to update… Yes, some resources to enhance your writing and presentation skills.

December 27

  • Your current grades has been updated at NetÀrea.
  • I’ll be in office (143E) from 10.00 to 12.00 to attend your queries or to give you back your projects by December 29 and 30, and by January 4.

December 23

NOTE: Drive <L:\>is currently down. You better solve the project P11 and the P12 in your own hard-drive and when completed, upload your documents and zipped files as usual at your ePortfolio page.

CSD final due dates:

  • P11: January 10 (4% if IT3 is passed)
  • P12: January 16 (4% if IT3 is passed)
  • Cooperative group video recording of an oral presentation of a course project (10%): January 19.
  • The ePortfolio eP2 self-assessment sheet (7 %) : January 19.

General guidelines on how to to organise and perform the 10 minutes group oral presentation of a course project (examples of oral presentations from previous CSD are still available in our (1), (2), etc.):

1. Rubric chart to organize and grade oral presentations

2. Another material that can help you on oral presentations.

3. Oral presentation resources from the EETAC library. This an example of commercial software that can help you to organise and render the video: Camtasia.

December 21

These are the IT3a, IT3b. The idea of designing a simple remote control that can be enhanced in successive stages. Second chance exams for IT2 and IT3 is January 10.

finals

  • You still have time to answer the questionnaires giving opinions on the subjects you are matriculated. Thank you for your participation.

enquesta

December 5

Your marks for IT2 and projects P5, P6, P7 and P8 are at the NetArea. Remember that project marks (P5 to P8) are provisional until you get a pass in IT2: You’ll have a second chance exam by January, 10: finalsHence, some of you have to pay special attention to these last weeks to consolidate your performance.

November 30

 

  • The anonymous UPC questionnaire are online, so please, be kind to answer it expressing your opinions and comments respecting CSD and your lecturer. Thank you very much for your participation.

enquesta

November 27

A new NOTE: The disk <L:\> is working again, however, let’s keep the new due date for the P8.

November 26

A new NOTE: Hi, yesterday I thought that the <L:\> problem was to be solved in the same day, and posted the note below, but I see that we’re not going to have it solved until the next week. So, let’s proceed as in other similar situations, let’s delay the due date of P8 one week, so it’ll be the next December 5.

By the way, well, let’s have the IT2 next week as stated. I see that on Monday, better if all of us save a copy of all our files and projects in our hard-disk or better at Dropbox/Onedrive or somewhere similar, so that we won’t have to rely so much in this <L:\> because I see that it goes failing time to time, precisely on weekend where the service is not attended but we’re studying the same. We’ll have to go finding solutions when problems arise. That’s how it works. Remember that you have to zip all your projects once finished and place them safely in your ePortfolio, which is already a good archive system in case you need to recover them for some reason.

And yes!, thank you for your email feedback which is helping me very much to get everything organised and up to date.

November 25

NOTE: This evening, something is wrong with the “L:\” drive, it has stopped working. I’ll talk to the CBL Àrea Tècnica to see what they can do.
But, by now, you should have many of your files archived in your hard disk or even better, in your e-Portfolio, so, you may try to solve the problem using your “C:\CSD\P8” instead of your “L:\CSD\P8”, and copy everything there when it works again. Or imagine any solution you infer to bypass this technical problem.

But remember that this P8 is the last of a series and of Chapter 2, and in some way it has no end, hence, don’t get too much worried about it. I recommend you to invest in it 4-5 hours of study time as usual, trying to do your best accordingly to the plan and grading list proposed. I mean that don’t try to get a 10 if it means that you have to leave other subjects unattended.

November 24

Due date for sending by email the self-assessment eportfolio EP1 is December 1.

November 7

Once published your grades for the projects P1-P4 and the IT1 exam, some you have to change the way you are coursing CSD. Start asking questions and annotating the important concepts we’ll solve in laboratory and class.

November 4

This is the second chance exam IT1.

Generate a group ePortfolio using the Google Sites tool and this instructions and send me the link, so you’ll have an archive location to store your projects and reflection on the course.

October 24

This is the IT1 (v1) and the IT1 (v2), discussion of its internal architecture.
In November 4, we’ll have a 2nd chance exam to pass or improve the IT1:

exam_1And January 10 is the second chance for the IT2 and IT3:

finals

NOTE: Please, take the IT1 2nd chance exam seriously, because if not, your projects P1 .. P4 will be downgraded to a 4. During this exams week come to my office to ask questions or whatever you need to understand the problems. For instance:

  • How to build a logic circuit using Buffer/NOT-OR-AND or Buffer/NOT-AND-OR gates?
  • How to build a circuit using only NOR or only NAND logic gates? How many VHDL files will contain the project? The VHDL description of the circuit, is behavioural or structural?
  • How to use multiplexers to build logic functions? Is it a project based on a single VHDL file or a multiple file project (hierarchical)?
  • How to implement a large decoder (or multiplexer, encoder, one’s counter, adder, comparator, etc.) using smaller blocks of the same kind and logic? Which is the same as how to expand circuits? How many files will contain the project of such hierarchical circuits?
  • How to use decoders to build logic functions? How many VHDL files will contain the project?
  • How to calculate the worse case scenario representing the longest transmission time and thus the highest frequency of operation?
  • How to interpret the Minilog output table format to deduce the minimised expressions SoP or PoS?
  • How to draw the truth table from WolframAlpha results (rearrange inputs order)?
  • How to operate (add/subtract) signed integers of N-bits using the 2C? Why the operation can result in overflow?
  • If the circuit internal architecture is given, can you calculate the outputs of the circuit driving the inputs with some example vector and obtaining the values in every wire?
  • How to represent a timing diagram of a given circuit to show how it works and be able to translate it later in a VHDL test bench to perform a simulation?
  • How to obtain a SoP or a PoS using Boolean Algebra from the circuit’s equation?
  • How to obtain maxterms or minterms (so, the truth table) if the SoP or the PoS is given?
  • etc.

 

September 12

CSD course starts in lab L129B (09:30, class 3GM11; 13:00, class 3GM12).

 

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July 2016

Curs de Raspberry Pi

 

 

 

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Course 15-16 Q2

June 6

The second chance IT2 – IT3.

May 24

This is the IT3, and in June 6, we’ll have a 2nd chance exam for the IT2 and IT3.

exam

IMPORTANT: The due date to upload the P12, your eP and the eP assessment sheets 1 and 2, and the video oral presentation of your project is Juny 11.

May 9:

Avui s’obre el període per a què els estudiants omplin les enquestes UPC sobre professors i assignatures: https://e-enquestes.upc.edu. And so, please, open the application in any computer or mobile device to fill in the questionnaire regarding this subject CSD. Thank you very much for your participation.

May 3:

This is the IT2.

April 8:

This is second chance test IT1R.

April 5:

Hi students,

Now is midterm, and I like to congratulate you that this course is going on quite well. I’m satisfied to see that you are engaged and doing mostly what is expected on the weekly projects and getting good marks. So, let’s hope that you continue this way to the end.

Some of you have to do the second chance exam IT1 by Friday 8, and some of you can optionally try to get better scores.

On the other hand, it seems that a few of you have decided to drop, and I have to tell you that yet you’re still in time to engage again in the course due to the way it is organised week by week. I know that you can do it. Come back to class and participate, you know that I can attend you as well in office time if necessary.

Remember that the objectives of this course include the specific content (combinational circuits, sequential systems and micro-controllers) as well as cross-curricular skills like teamwork, project management, efficient use of equipment and instruments (EDA tools and subject-related software), efficient oral and written communication, English and self-directed learning. This is why we have set this formative assessment scheme in which you have to hand in your projects and explain them weekly in order to get the marks that you are also invited to discuss.

I wish you good luck in your exams and regards,

March 29

This is test IT1 that we had today (commented solution).

March 28:

Information on how to prepare your group ePortfolio is available here.

March 7:

Citrix technology: A virtual PC in Windows 7 with all the EETAC software. The tutorial for installation.

February 15:

This new EETAC tool will enable conversation on CSD subject. The posts will guide you to day to day information on the course and on how to solve problems and projects. Ask for registration in this blog (use your @estudiant.upc.edu address) to be able comment the posts. Surely your questions & answers will help your team and classmates to perform better. Older posts can be reached using the search tool.

Please: Use this rules to email me. Get used to your professional email address and organise your computer and mobile devices to be able to send emails from your UPC address.

2nd chance exams:

ex1

ex2